The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 64 GB/s.

Download this eBook to:

  • Learn how GDDR6 can meet the demand for increased bandwith across multiple market verticals
  • Understand and address the challenges of GDDR6 PHY design
  • See how the Rambus GDDR6 PHY IP Core can be optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions
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