SerDes Signal Integrity Challenges at 28Gbps and Beyond

After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization to correct. In addition, channel loss and reflections (noise) at increased data rates and noise complicate forward error correction.

While 56 Gbps PAM4 doubles the number of bits in serial data transmissions by increasing the number of levels of pulse-amplitude modulation, it does so at the cost of noise tolerance, or 33% of amplitude compared to NRZ. As with NRZ, PAM4 signals are also affected by jitter, channel loss and inter-symbol interference. In addition, measurements for the three eyes are further complicated by new receiver behavior, such as three slicer thresholds, individual slicer timing skew, equalization and clock and data recovery. Moreover, moving to 56G PAM4 immediately causes a loss of 9.6 dB, but is still preferred if the channel loss at NRZ Nyquist frequency is too significant.

Engineers have adapted to the various challenges of designing high speed SerDes by upgrading the package design, thereby addressing high frequencies and tight electrical performance requirements. In addition, the engineers have placed an emphasis on detailed modeling and designing highly programmable circuits, debug interfaces and utilities that enable the easy collation of important analog and digital information. From the perspective of a customer, design experience and the ability to execute in a timely manner are essential. It is therefore critical for SerDes vendors to include a range of experts at various stages of the design, such as package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists.

This paper will discuss the various challenges of designing high speed SerDes, as well as the importance of detailed modeling and design of highly programmable circuits and debug interfaces

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