After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization to correct.
This paper will discuss the various challenges of designing high speed SerDes, as well as the importance of detailed modeling and design of highly programmable circuits and debug interfaces.
- NRZ and PAM4
- Simulation and modeling
- Embedded tools and design recommendations
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