Crypto Accelerator Hardware Cores

Rambus Crypto Accelerator Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software. This allows the CPUs to focus on other important tasks. These superior performance cores are easily integrated into SoCs and FPGAs, and support Suite-B industry standard cryptographic algorithms and random number generators such as AES, 3DES, SHA-2, HMAC, RBG, ChaCha20, and Whirlpool across multiple operating modes. The cores are validated to FIPS 140-2 CAVP.

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