Design complexity for advanced SoCs rises with each new process node, performance increase, and addition of new IP blocks. Designers are faced with increasing challenges to confidently verify and validate functionality of their chips.
The LabStation Validation platform is a comprehensive tool suite for the rapid bring-up, validation and characterization of complex low-power, high-performance memory and serial link IP. It is designed to be easy to use and improve productivity while providing improved accuracy of test results and confidence is system performance.
The platform features an enhanced user interface to improve the usability and control of IP including access to on-chip circuits, on-board devices, measurement equipment and 3rd party tools. This helps customers validate our R+ Memory and Serial Link PHYs to enhance the quality and reduce time-to-market of their chips and systems. The suite is proven in high-volume applications and offers an effective set of on-chip, automated test tools for validating the designs of advanced memory sub-systems and high-speed serial links for production.
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